In recent years, an amount of data to be transferred by a bus in an LSI (Large Scale Integration) increases as a data amount to be handled in the LSI increases. Therefore, the technique in which data are transferred among bus slaves at a higher speed is demanded. In a conventional information processing apparatus, a data transfer among the slaves is carried out through a bus master. In this case, 2-cycle transfer of the data transfer from a source slave to the bus master and the data transfer from the bus master to a destination slave is carried out. Therefore, even if the transfer efficiency is improved, 2 transfer cycles are required at minimum.
As the technique for carrying out data transfer at higher speed, a technique of the 1-cycle transfer is disclosed in JP 2006-146817A (Patent Literature 1), in which data is directly transferred from the source slave to the destination slave without passing through the bus master.
FIG. 1 is a block diagram showing a circuit configuration of a memory control system in Patent Literature 1. As shown in FIG. 1, an LSI 100 is provided with a CPU 110, a memory controller (MEMC) 160 and a system bus 150. The CPU 110 is connected with the system bus 150. The memory controller 160 controls an external ROM 200 and an external DRAM 300. The memory controller 160 is connected with the external ROM 200 and the external DRAM 300 by an address bus 161 passing through common external terminals. In the same way, the memory controller 160 is connected with the external ROM 200 and the external DRAM 300 by a data bus 162 passing through common external terminals. Moreover, the memory controller 160 outputs a ROM control signal 163 to control the external ROM 200 through an independent external terminal. In the same way, the memory controller 160 outputs a DRAM control signal 164 to control the external DRAM 300 through an independent external terminal. These control signals 163 and 164 include the minimum signals necessary to control the general ROM and DRAM, and the external ROM 200 and the external DRAM 300 can be controlled independently by these signals according to the memory access from the CPU 110.
FIG. 2 is a block diagram showing a specific connection relation of the LSI 100, the external ROM 200, and the external DRAM 300 in the memory control system of Patent Literature 1. Here, the external ROM 200 is a page ROM of 16 Mbits (1 Mword×16 bits). The address bus 161 of 20 bits in width is provided as a 20-bit physical address just as it is. On the other hand, the external DRAM 300 is a 64-Mbit DRAM (4-Mword×16 bits). A column address is of 12 bits, and a row address is of 10 bits. Only the lower 12 bits on the address bus 161 are supplied as a physical address. Also, the data bus 162 is of 16 bits in width and is connected with both of the external ROM 200 and the external DRAM 300. The ROM control signal 163 is composed of signals of CS#, RD# and is independently connected with the external ROM 200. Also, in the same way, the DRAM control signal 164 is composed of signals of RAS#, LCAS#, UCAS#, WE#, and OE# and is independently connected with the external DRAM 300.
FIG. 3 is a diagram showing an example of a memory map of the memory control system in Patent Literature 1. As shown in FIG. 3, the external ROM 200 is mapped on the memory map from an address 0xF000—0000 to an address 0xFFFF_FFFF. Also, the external DRAM 300 is mapped on the memory map from an address 0x0000—0000 to an address 0x3FFF_FFFF. Here, to facilitate the explanation, it is supposed that initialization code to initialize a system is written in 64 KB from the address 0xF000—0000 to the address 0xF000_FFFF and instruction code to actually control the system is written in 1 MB from an address 0xF001—0000 to an address 0xF010_FFFF in the external ROM 200. Moreover, the instruction code copied from the external ROM 200 to the external DRAM 300 is only 1 MB of the above-mentioned instruction code which actually controls the system, and this instruction code is supposed to be described in memory-allocatable contents non-dependent to absolute address.
Next, in the memory control system of Patent Literature 1, the copying operation the instruction code from the external ROM 200 to the external DRAM 300 when the system starts will be described.
At first, when an initial reset such as power-on-reset from outside is carried out, the CPU 110 first fetches the instruction code in a memory space according to an internal reset vector. At this time, a non-volatile memory which can hold the instruction code in the initial state is only the ROM. Therefore, the reset vector of the CPU 110 points out the address 0xF000—0000 which is the head address of the external ROM 200, and it is supposed that the instruction code is written in the external ROM 200 in order from the address pointed out by the reset vector.
Therefore, after the reset cancellation, the CPU 110 accesses the external ROM 200 through the system bus 150 and the memory controller 160, and fetches the initialization code for initializing a system from the address 0xF000—0000 of the memory map in order. After the fetching of this initialization code, the CPU 110 implements the initialization of the system according to the contents of the initialization code. Here, an address to access the external ROM 200 and data read from the external ROM 200 are supplied to the external DRAM 300 at the same time, but do not affect any influence because the DRAM control signal 164 is asserted not to permit the access.
When the initialization of the system completes, the CPU 110 requests the memory controller 160 to copy the instruction code written in the external ROM 200 to the external DRAM 300. At this time point, the operation of the CPU 110 is implemented completely according to the instruction code fetched from the external ROM 200. Hereinafter, the copying procedure of the instruction code by the memory controller 160 will be described.
First, the CPU 110 sets to the memory controller 160, a first address 0xF001—0000 of the instruction code written in the external ROM 200 as a source address, a first address 0x0000—0000 of the external DRAM 300 as a destination address, and a total byte count (1 MB) of the instruction code to be copied as a transfer length. Here, the column address of the external DRAM 300 and lower 12 bits, corresponding to the column address, of the address of the external ROM 200 must be equal to each other to produce a replica of the instruction code. Therefore, it is supposed that the addresses are preset in such a manner that the lower 12 bits of the transfer addresses are equal to each other, or only lower 12 bits of either of the destination address or the source address is validated. The setting values are previously written in the external ROM 200 together with the instruction code, and the CPU 110 can set them to the memory controller 160 by reading from the external ROM 200.
When the above mentioned setting are complete, the CPU 110 instructs the start to the memory controller 160, so that the instruction code is copied from the external ROM 200 to the external DRAM 300 independent from the CPU 110.
The operation when the instruction code of the address 0xF001—1234 of the external ROM 200 is copied to the address 0x0000—1234 of the external DRAM 300 will be described.
FIG. 4 is a diagram showing timing charts when the instruction code is copied in the memory control system of Patent Literature 1. First, the memory controller 160 outputs the row address 0x001 for the external DRAM 300 onto the address bus 161 at the timing T2 and sets the row address valid by asserting RAS# at the timing T3. At this time, only lower 10 bits on the address bus 161 are valid. After that, the identical address 0x11234 for the external ROM 200 and the external DRAM 300 is outputted on the address bus 161 from the timing T4. As shown in FIG. 2, all of the 20 bits of the address bus 161 are validated to the external ROM 200, but only lower 12 bits corresponding to the column address are validated to the external DRAM 300. Therefore, in this case, the column address to the external DRAM 300 is 0x234.
Next, a read request from the address 0x11234 is issued to the external ROM 200 by asserting CS# and RD# at the timing T6. After a predetermined time, the external ROM 200 outputs read data onto the data bus 162. At this time, the memory controller 160 requests a write operation to the address 0x01234 by asserting UCAS#, LCAS#, and WE# to the external DRAM 300 at the timing T8. Thus, the instruction code on the data bus 162 is directly written in the external DRAM 300. Since then, the source address and the destination address are incremented and the read operation and the write operation for the instruction code are repeated in the same way.
When a DMA transfer completes, the memory controller 160 notifies a DMA transfer completion to the CPU 110. When receiving the DMA transfer complete notice, the CPU 110 branches to the first address 0x0000—0000 of the instruction code copied to the external DRAM 300. By this, the CPU 110 fetches the instruction code from the external DRAM 300 in order. Since this, the CPU 110 fetches the instruction code from only the external DRAM 300 so that the latency of the external memory access containing the fetching of the instruction code is reduced and the processing speed of the whole system can be sped up.
As a related technique, a non-volatile semiconductor memory device is disclosed in JP 2008-146773 A (Patent Literature 2). This non-volatile semiconductor memory device is provided with a first semiconductor chip containing a first memory and a second semiconductor chip containing a second memory. After starting an instruction for executing a read enable operation as a write enable operation in the second memory as a copy destination, the read enable operation is performed and the data of the first memory as a copy source is copied to the second memory.
Also, a non-volatile semiconductor memory device is disclosed in JP 2007-164895A (Patent Literature 3: corresponding U.S. Pat. No. 7,486,569B2). This non-volatile semiconductor memory device has a plurality of memory chips. In this non-volatile semiconductor memory device, after starting an instruction for executing a read enable operation as a write enable operation in the memory chip of a copy destination, the read enable operation is carried out when the data copy is carried out among the plurality of memory chips.